The present invention relates generally to silicon-on-insulator (SOI) field effect transistors (FETs) and specifically to pass gate leakage in gated devices.
In SOI devices such as metal oxide semiconductor (MOS) FETs, the body of the device is disposed on an insulator rather than wafer, and hence is xe2x80x9cfloatingxe2x80x9d as compared to conventional bulk devices. This floating body leads to leakage mechanisms that do not occur in bulk devices. One such leakage mechanism that occurs in SOI FETs is referred to as pass gate leakage (PGL).
In an n-channel FET (NFET), when the FET is off and has a zero potential at the gate terminal, and the source and the drain are at the supply potential (+V or Vdd), the silicon-insulator interface will be in the accumulation mode. In accumulation mode, the body develops a positive potential after a sufficient period of time. If the source is then suddenly dropped to zero potential, the source-body junction is forward biased, which allows holes to flow to the source and electrons to flow to the body. The electrons that flow to the body (and eventually to the drain) act as a collector current for the lateral NPN bipolar device.
In addition to the collector current, the forward bias of the source-body junction temporarily causes the threshold voltage of the device to decrease, which results in increased sub-threshold current. This current, in combination with the collector current, form an undesirable drain current that can impact the correct functioning of the FET. For example, pass gate leakage reduces noise immunity by allowing unwanted signals to pass through the device. What is needed in the art is a method of monitoring pass gate leakage in SOI devices, such as NFETs, that exhibit such unwanted leakage.
An embodiment of the present invention is a wafer processing test circuit comprising a plurality of pass gates having varying channel widths, a plurality of latches each connected to one of said pass gates, each of said latches receiving a leakage signal from its connected pass gate, an input circuit for supplying a test signal to said plurality of pass gates, said test signal having a preselected magnitude, wherein said plurality of pass gates outputs a leakage signal to its connected latch in response to said test signal, thereby causing said latches to assume one of a triggered state and an untriggered state, and storage coupled to said plurality of latches for storing one of said triggered state and untriggered state for each of said latches.
Another embodiment of the present invention is a method for testing for pass gate leakage in devices on a wafer comprising applying a test signal of a preselected magnitude to a plurality of pass gates having varying channel widths, outputting a leakage signal from each of said pass gates, receiving said leakage signals at a plurality of latches each connected to one of said pass gates, wherein said leakage signals are not all sufficient to trigger their connected latches, and storing triggered and untriggered latch states in storage coupled to said latches.